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K4S281632D-L1H Datasheet 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

Manufacturer: Samsung Semiconductor

Download the K4S281632D-L1H datasheet PDF. This datasheet also includes the K4S variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (K4S-28163.pdf) that lists specifications for multiple related part numbers.

General Description

The K4S281632D is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Overview

K4S281632D CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Rev.

0.1 Sept.

2001 * Samsung Electronics reserves the right to change products or specification without notice.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K cycle.